Improved Transistor Degradation Models to predict Circuit Lifetime

© Fraunhofer IIS/EAS
Fig. 1: Distribution map of time constants for gate oxide traps.
© Fraunhofer IIS/EAS
Fig. 2: The developed compact model (solid lines) fits the voltage shift relaxation characterized by measurements (circles) as well as detailed TCAD results (dashes) at various stress times.
© Fraunhofer IIS/EAS
Fig. 3: Comparison of our fast compact model to a detailed TCAD model when a sine wave signal is applied.

Ongoing developments in manufacturing processes of integrated circuits have seen a progressive shrinking of the individual features. Ever smaller component sizes as well as new materials create physical effects that can actually hinder circuit operation. Process variations and parameter degradation are two significant examples of such effects. While variations lead to differences in the operation of individual circuits right after production, parameter degradations modify circuit properties over their functional life. Moreover, external environmental conditions like thermal or mechanical stress affect the electrical behavior of semiconductors.

As a consequence, there is a danger that integrated circuits can deviate significantly from several specified characteristics over their functional lifetime. This usually leads to failure of the electronic components during operation. This needs to be prevented, particularly for safety-critical systems, in order to avoid fatal failures in the field. Appropriate verification processes are required to cope with these effects already at the design stage.

Today’s design tools and environments need to be improved to ensure that extended lifetime targets can be verified for each circuit under the conditions of its intended application.

In order to avoid failures of circuits during operation, it is important to understand the physical cause behind the parameter deviations. Furthermore, it is essential to analyze their influences on device and circuit behavior. This enables circuit designers to optimize the circuits to meet the specifications under the given application conditions.

The EU FP7 research project MoRV (“Modelling reliability under Variability”, grant agreement no. 619234) investigates in detail the physics of semiconductor degradation mechanisms and employs this knowledge into circuit level models.

The project contribution of Fraunhofer IIS/EAS was the development of an abstraction process to establish efficient compact models of real device behavior. This abstraction process was based on the whole spectrum of semiconductor physics including quantum effects. Extensive computations from a project partner provided a detailed understanding and statistical confidence. Proceeding from these analyses, the scientists of Fraunhofer IIS/EAS derived abstract models to represent the important features of device physics. The main challenge was to generate accurate transistor-level aging models that are fast enough to be used in simulations of full-chips comprising thousands of devices.


Technology-aware degradation model

In the analysis, we concentrated on one major degradation mechanism in advanced semiconductor technologies: negative bias temperature instability (NBTI). The origin of deviations from the device characteristics are defects in the gate oxide as well as in the interface to the silicon channel. These traps can be either charged or discharged, which affects the device threshold voltage and thereby overall circuit functionality. Charging and discharging occurs on a statistical basis and depends on device bias, device geometry and junction temperature. Extensive characterization of devices using a typical analog/mixed signal technology was done by a project partner for different values of the influencing factors. Statistical confidence was reached by performing a large number of TCAD (Technology CAD) simulations, which were calibrated with measured device characteristics. Unfortunately, stress measurements can only be executed for single devices, as electrical overstress is impossible for a functional circuit. TCAD simulations are highly time consuming and therefore allow analyzing device behavior only at short time scales - of the order of seconds. To determine the behavior of entire circuits or systems-on-chip, completely new approaches are needed that accelerate the simulation by several orders of magnitude, while maintaining comparable levels of accuracy.


Circuit level compact model

Based on detailed physical behavior, a mathematical model was established that represents the statistical probabilities of the charging and discharging processes including their voltage dependencies. For this mathematical representation in the form of an ODE (Ordinary Differential Equation) a very efficient solution was found using numerical integration. Depending on the size of the device in the technology at hand, the model takes a subset of defects from a large database and computes the change of the characteristics for the whole device. Due to its numerical efficiency the developed algorithm is able to predict the behavior of a circuit over several years of operation.


The current purely digital NBTI models account for only two stress levels. In contrast, the approach of Fraunhofer IIS/EAS is capable of taking truly analog signals (e.g. sine wave) into account and therefore applies to analog circuit design as well.



As a result of model development and efficient implementation, we demonstrated that detailed TCAD simulation outcomes as well as measurements can be accurately reproduced at the transistor level. As opposed to previous approaches, the model of Fraunhofer IIS/EAS allows simulations of several years of operation. This analysis can be done within milliseconds – as well as extensive statistical analysis for different defect configurations and device geometries.

This fast and efficient compact model for the NBTI degradation effect enables circuit designers to analyze the long-term behavior of a circuit under realistic load conditions during operation. Circuit optimization can be performed by assessing and reducing reliability margins and thereby avoiding unnecessary overdesign. At the same time functional verification assures reliable operation over the entire lifetime.